Is SMBus and I2C the same?
Both the SMBus and the I2C bus are two wire open collector buses with a high level of compatibility. In fact, mixing SMBus and I2C bus master and slave devices often works without any problems as long as no I2C master uses a clock speed above 100 kbit. While the I2C standard defines three speed grades – 100, 400 and 3200 kbit, SMBus devices are limited to 100 kbit. In most cases SMBus devices are used for control purposes requiring only a few bytes of data and therefore lacking the need for higher transfer speed.
The most significant difference between the two buses is the way error recovery is handled. The SMBus defines a time out for slave devices and therefore dictates a minimum clock speed of 10 kHz with a timeout at 35 ms.
In theory an I2C slave device could hold the clock line low for hours without violating the specification. All an I2C master can do to free a blocked bus is to attempt to move the clock line up and down and read back its value to see if the bus is (now) free.
With the timeout introduced for the SMBus slave devices are able (and requested) to reset their state machine after detecting the clock to be low for more than the timeout value. This results in a considerably improved error recovery capability of the bus.
Another significant difference is the definition of maximum bus termination and therefore the definition of maximum current for SMBus and I2C devices.
For SMBus devices the maximum current is defined at 350 µA while this value is 3 mA for I2C devices. This parameter implicitly defines the maximum termination (lowest resistor value) allowed for a given voltage. The obvious reason for the limitation in the SMBus specification is to relieve devices from having to sink a lot of current but there is also a draw back to a low resistor which is a higher impact of bus capacitance on the signal quality. This is in turn compensated by the limitation of the bus speed to 100 kHz.
A more academic difference between the two bus systems is a slightly different definition of high and low level for each voltage range. Since most devices fully release the bus to high level and pull it low (which is almost zero Volt), these limits are hardly ever exploited. Note that Tracii XL 2.0 allows an adjustment of logic levels.
General Call and Alert
The I2C standard defines a “General Call Address” 0 which allows simultaneous communication with multiple slaves. This feature is hardly ever used in practice and not present in the SMBus standard. Instead, the SMBus defines an Alert line which acts as an interrupt to the bus master. Upon receipt of an interrupt, the SMBus master can issue an Alert Response. This Alert Response is sent to address 0001 100, and any slave device that generated an interrupt attempts to identify itself by putting its own address on the bus. The device with the lowest address will dominate (due to the open-collector bus). If it is serviced and cleared, the master can repeat the process and work up through any other interrupts that may have occurred. This is similiar to the well-known daisy chain handling of interrupts.
In addition there are some other differences between the specifications which are hardly ever noted. One of them is the ability of an SMBus master to fully power down the bus (switch off termination) while no communication is going on. This is especially relevant when an non-SMBus-aware device attempts to detect the power on event as a start or stop condition.