Can I Expect 50-50 Duty Cycle ?
There is a 14.5 microsecond pulse width between the 8th data bit and acknowledge bit at 100 KHz when it should be 5 microseconds. It was said that this bug will be taken care of in the next release.
This is *not* a bug. The behaviour of Tracii XL conforms to the I2C specification. The I2C bus does not guarantee an exact timing for the clock.