04-03-04 03:33
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There is a 14.5 microsecond pulse width between the 8th data bit and acknowledge bit at 100 KHz when it should be 5 microseconds. It was said that this bug will be taken care of in the next release. When will this next release be. I need it this week
This is *not* a bug. The behaviour of Tracii XL conforms to the I2C specification. The I2C bus does not gurantee an exact timing for the clock.
The I2C specification can be found here:
http://www.telos.de/tracii/i2c_e.htm
We have released a new version of I2C Studio (1.5) yesterday. This version contains an update for Tracii XL, which improves the SCL timining.
You can find this update at our download page:
https://telos-www2.telos.de/?id=46
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